As process technologies have scaled to smaller feature sizes, the size of transistors has scaled faster than the size of interconnecting wires. Therefore, wires take proportionally more area and the die area silicon cost benefits of process technology scaling is limited by wires.
Many chips, particularly ones oriented towards signal processing or highly parallel processing, comprise thousands of binary digital multipliers. Each multiplier comprises at least some of half adders, full adders, counters, compressors, and a carry propagate adder. Different organizations of gates and wires within each such component, and their interconnectivity, affect the total logic switching delay and wire density.
An 8×8 multiplier is a common, useful logic component within many chips. It can be used alone for multiplying 8-bit numbers to generate a 16-bit result, or as part of a larger multiplier for multiplying larger numbers. Conventional 8×8 multipliers have a middle column of partial product summation that has a height of 8 terms, which limits the multiplier logic speed. Using conventional compressors on the middle column requires undesirable numbers of inter-column wires, which reduce wire density, and therefore increase silicon area cost.
What is needed is an 8×8 multiplier with fewer wires, especially wires crossing columns of partial product summation.